Design for test (DFT) approach is a scan chain based design for testing integrated circuits. Scan chain based design is a preferred mechanism for diagnosis of manufacturing defects. Scan chain based diagnosis is fast and efficient for large integrated circuits thus improving the product yield. The scan chain based diagnosis identifies root cause of logic failure in a circuit in the IC. During IC test, the scan chains are also tested to ensure that scan chains are defect free. Any defect in the scan chains become cumbersome to debug. Conventional method of debugging scan chains includes SOM (scanning optical microscopy) or EMMI (emission microscopy). These debugging techniques are expensive and time consuming. Pattern dependent failure diagnosis is also used to debug scan chain defects. Automatic test pattern generation (ATPG) tools are used to generate multiple patterns to be run on the IC. In case of a scan chain failure, design support tools which know the whole design structure are required to use ATPG tools, and these design support tools are not available either. Thus, a design is needed that facilitates faster scan chain diagnosis.